what does it mean to be byte addressable

In computer architecture, word addressing means that addresses of retention on a computer uniquely place words of memory. It is usually used in contrast with byte addressing, where addresses uniquely place bytes. Virtually all modern calculator architectures use byte addressing, and word addressing is largely merely of historical involvement. A computer that uses word addressing is sometimes chosen a give-and-take auto.

Tables showing the same data organized nether byte and discussion addressing

Nuts [edit]

Consider a computer which provides 524,288 (2¹⁹) $.25 of memory. If that memory is arranged in a byte-addressable apartment address space using eight-bit bytes, then there are 65,536 (ii¹⁶) valid addresses, from 0 to 65,535, each cogent an independent 8 bits of retentiveness. If instead it is bundled in a word-addressable flat address infinite using 32-chip words, then there are 16,384 (two¹⁴) valid addresses, from 0 to 16,383, each denoting an independent 32 bits.

More more often than not, the minimum addressable unit (MAU) is a property of a specific memory abstraction. Unlike abstractions within a figurer may use different MAUs, even when they are representing the same underlying memory. For case, a computer might use 32-scrap addresses with byte addressing in its instruction set, just the CPU'due south cache coherence system might work with memory just at a granularity of 64-byte cache lines, allowing any particular enshroud line to be identified with merely a 26-scrap accost and decreasing the overhead of the cache.

The address translation washed by virtual memory often affects the structure and width of the accost space, merely it does non change the MAU.

Merchandise-offs of different minimum addressable units [edit]

The size of the minimum addressable unit of retentiveness can accept complex trade-offs. Using a larger MAU allows the same amount of memory to be covered with a smaller address, which can substantially decrease the retentivity requirements of a program. However, using a smaller MAU makes it easier to work efficiently with pocket-size items of data.

Suppose a program wishes to store one of the 12 traditional signs of Western star divination. A single sign can be stored in iv bits. If a sign is stored in its own MAU, and then iv bits will be wasted with byte addressing (fifty% efficiency), while 28 $.25 volition be wasted with 32-flake discussion addressing (12.5% efficiency). If a sign is "packed" into a MAU with other data, so it may be relatively more than expensive to read and write. For example, to write a new sign into a MAU that other data has been packed into, the computer must read the current value of the MAU, overwrite merely the appropriate bits, and so shop the new value back. This will be especially expensive if it is necessary for the programme to allow other threads to meantime modify the other data in the MAU.

A more than common example is a string of text. Common string formats such as UTF-8 and ASCII store strings as a sequence of 8-bit lawmaking points. With byte addressing, each lawmaking point can be placed in its own independently-addressable MAU with no overhead. With 32-bit word addressing, placing each code bespeak in a divide MAU would increase the memory usage by 300%, which is non viable for programs that work with big amounts of text. Packing next code points into a single word avoids this toll. Nonetheless, many algorithms for working with text prefer to exist able to independently address lawmaking points; to do this with packed lawmaking points, the algorithm must use a "wide" accost which also stores the showtime of the graphic symbol within the word. If this wide address needs to exist stored elsewhere within the plan's retentivity, it may require more memory than an ordinary accost.

To evaluate these effects on a complete program, consider a web browser displaying a big and complex page. Some of the browser's memory will be used to shop elementary data such equally images and text; the browser will likely choose to store this data as efficiently as possible, and it will occupy about the same amount of retentivity regardless of the size of the MAU. Other memory volition represent the browser's model of various objects on the page, and these objects volition include many references: to each other, to the image and text information, and and then on. The amount of memory needed to shop these object will depend greatly on the address width of the computer.

Suppose that, if all the addresses in the program were 32-fleck, this web page would occupy about 10 Gigabytes of memory.

• If the web browser is running on a computer with 32-bit addresses and byte-addressable memory, the address space volition cover four Gigabytes of retentiveness, which is bereft. The browser will either be unable to display this folio, or it will need to be able to opportunistically move some of the data to slower storage, which will essentially hurt its performance.
• If the spider web browser is running on a computer with 64-flake addresses and byte-addressable retentivity, it volition require substantially more than memory in order to store the larger addresses. The exact overhead will depend on how much of the 10 Gigabytes is simple data and how much is object-like and dense with references, but a figure of 40% is not implausible, for a total of xiv Gigabytes required. This is, of course, well within the capabilities of a 64-bit address space. However, the browser volition by and large exhibit worse locality and brand worse use of the computer's memory caches within the computer, assuming equal resources with the alternatives.
• If the spider web browser is running on a estimator with 32-bit addresses and 32-bit-word-addressable memory, it will likely require extra memory considering of suboptimal packing and the need for a few broad addresses. This touch on is likely to be relatively minor, as the browser will employ packing and non-wide addresses for virtually of import purposes, and the browser will fit comfortably within the maximum addressable range of 16 Gigabytes. However, at that place may be a meaning runtime overhead due to the widespread apply of packed data for images and text. More importantly, 16 Gigabytes is a relatively low limit, and if the spider web folio grows significantly, this estimator will exhaust its accost space and begin to have some of the same difficulties as the byte-addressed computer.
• If the web browser is running on a computer with 64-bit addresses and 32-bit-word-addressable memory, it volition suffer from both of the above runtime overheads: it crave substantially more memory to accommodate the larger 64-bit addresses, hurting locality, while also incurring the runtime overhead of working with extensive packing of text and epitome data. Give-and-take addressing means that the plan tin can theoretically address up to 64 Exabytes of memory instead of only 16 Exabytes, but since the program is nowhere almost needing this much memory (and in practice no real computer is capable of providing it), this provides no benefit.

Thus, word addressing allows a reckoner to address substantially more memory without increasing its address width and incurring the corresponding large increase in memory usage. However, this is valuable only within a relatively narrow range of working fix sizes, and it can introduce substantial runtime overheads depending on the awarding. Programs which exercise relatively piffling piece of work with byte-oriented data like images, text, files, and network traffic may exist able to do good most.

Sub-word accesses and wide addresses [edit]

A program running on a estimator that uses word addressing can still piece of work with smaller units of memory by emulating an admission to the smaller unit of measurement. For a load, this requires loading the enclosing discussion then extracting the desired bits. For a shop, this requires loading the enclosing word, shifting the new value into identify, overwriting the desired bits, and so storing the enclosing word.

Suppose that 4 sequent code points from a UTF-8 string need to exist packed into a 32-bit word. The commencement code point might occupy bits 0–seven, the second eight-xv, the 3rd 16–23, and the fourth 24–31. (If the memory were byte-addressable, this would be a piddling endian byte order.)

In guild to clearly elucidate the code necessary for sub-word accesses without tying the case too closely to whatsoever particular discussion-addressed architecture, the post-obit examples use MIPS associates. In reality, MIPS is a byte-addressed architecture with straight support for loading and storing 8-bit and 16-scrap values, but the example volition pretend that information technology just provides 32-bit loads and stores and that offsets within a 32-fleck discussion must be stored separately from an address. MIPS has been chosen because it is a simple assembly language with no specialized facilities that would brand these operations more than convenient.

Suppose that a programme wishes to read the third code point into register r1 from the word at an accost in register r2. In the absence of any other support from the instruction set, the program must load the full give-and-take, correct-shift by 16 to driblet the first two code points, and then mask off the 4th code point:

          ldw  $r1, 0($r2)        # Load the full discussion   srl  $r1, $r1, xvi       # Shift right by 16   andi $r1, $r1, 0xFF     # Mask off other code points

If the kickoff is not known statically, but instead a bit-start is stored in the register r3, a slightly more than complex approach is required:

          ldw  $r1, 0($r2)        # Load the full word   srlv $r1, $r1, $r3      # Shift right by the scrap offset   andi $r1, $r1, 0xFF     # Mask off other code points

Suppose instead that the program wishes to assign the lawmaking indicate in annals r1 to the third code point in the word at the accost in r2. In the absence of any other support from the pedagogy set, the program must load the full word, mask off the old value of that code point, shift the new value into place, merge the values, and store the total word back:

          sll  $r1, $r1, xvi       # Shift the new value left by xvi   lhi  $r5, 0x00FF        # Construct a abiding mask to select the tertiary byte   nor  $r5, $r5, $zero    # Flip the mask so that it clears the 3rd byte   ldw  $r4, 0($r2)        # Load the full word   and  $r4, $r5, $r4      # Clear the third byte from the give-and-take   or   $r4, $r4, $r1      # Merge the new value into the word   stw  $r4, 0($r2)        # Store the result as the total word

Once again, if the outset is instead stored in r3, a more complex approach is required:

          sllv $r1, $r1, $r3      # Shift the new value left by the bit offset   llo  $r5, 0x00FF        # Construct a constant mask to select a byte   sllv $r5, $r5, $r3      # Shift the mask left by the fleck offset   nor  $r5, $r5, $zero    # Flip the mask so that it clears the selected byte   ldw  $r4, 0($r2)        # Load the full word   and  $r4, $r5, $r4      # Clear the selected byte from the discussion   or   $r4, $r4, $r1      # Merge the new value into the word   stw  $r4, 0($r2)        # Store the effect equally the full discussion

This code sequence assumes that another thread cannot change other bytes in the discussion concurrently. If concurrent modification is possible, then one of the modifications might exist lost. To solve this problem, the last few instructions must be turned into an diminutive compare-exchange loop so that a concurrent modification volition just cause information technology to echo the operation with the new value. No retention barriers are required in this case.

A pair of a word address and an outset within the word is called a wide address (also known as a fat address or fat pointer). (This should not be dislocated with other uses of broad addresses for storing other kinds of supplemental data, such as the bounds of an assortment.) The stored offset may be either a scrap offset or a byte kickoff. The code sequences above benefit from the offset being denominated in bits because they use it as a shift count; an architecture with direct support for selecting bytes might adopt to but shop a byte offset.

In these code sequences, the boosted offset would have to be stored alongside the base address, effectively doubling the overall storage requirements of an address. This is not always true on word machines, primarily because addresses themselves are frequently non packed with other data to make accesses more efficient. For example, the Cray X1 uses 64-bit words, just addresses are only 32 bits; when an address is stored in memory, it is stored in its own discussion, and so the byte offset can be placed in the upper 32 $.25 of the word. The inefficiency of using broad addresses on that organization is just all the extra logic to manipulate this offset and extract and insert bytes within words; information technology has no memory-use bear on.

[edit]

The minimum addressable unit of a computer isn't necessarily the aforementioned as the minimum retentivity access size of the computer'southward instruction set. For example, a estimator might use byte addressing without providing any instructions to directly read or write a single byte. Programs would be expected to emulate those operations in software with bit-manipulations, just like the example code sequences in a higher place do. This is relatively mutual in 64-bit computer architectures designed as successors to 32-bit supercomputers or minicomputers, such the DEC Alpha and the Cray X1.

The C standard states that a pointer is expected to have the usual representation of an address. C also allows a pointer to be formed to any object except a bit-field; this includes each individual element of an array of bytes. C compilers for computers that use word addressing oftentimes use unlike representations for pointers to different types depending on their size. A pointer to a type that's big plenty to fill up a word will be a unproblematic address, while a pointer such equally char* or void* will be a wide pointer: a pair of the address of a word and the offset of a byte within that word. Converting betwixt pointer types is therefore not necessarily a picayune functioning and can lose information if washed incorrectly.

Because the size of a C struct is not e'er known when deciding the representation of a arrow to that struct, information technology is non possible to reliably utilize the rule above. Compilers may need to marshal the start of a struct and so that information technology can utilize a more efficient pointer representation.

Examples [edit]

• The ERA 1103 uses word addressing with 36-bit words. Only addresses 0-1023 refer to random-access retention; others are either unmapped or refer to drum memory.
• The PDP-10 uses discussion addressing with 36-scrap words and 18-flake addresses.
• Most Cray supercomputers from the 1980s and 1990s use word addressing with 64-chip words. The Cray-ane and Cray X-MP use 24-bit addresses, while most others employ 32-bit addresses.
• The Cray X1 uses byte addressing with 64-bit addresses. It does not direct support retention accesses smaller than 64 bits, and such accesses must be emulated in software. The C compiler for the X1 was the starting time Cray compiler to support emulating 16-flake accesses.^[1]
• The DEC Alpha uses byte addressing with 64-fleck addresses. Early Alpha processors do not provide whatsoever direct back up for 8-chip and xvi-bit retentiveness accesses, and programs are required to e.one thousand. load a byte by loading the containing 64-fleck word and and so separately extracting the byte. Because the Alpha uses byte addressing, this commencement is however represented in the least significant bits of the address (rather than separately equally a wide accost), and the Alpha conveniently provides load and shop unaligned instructions (ldq_u and stq_u) which ignore those bits and simply load and shop the containing aligned word.^[2] The later byte-word extensions to the architecture (BWX) added viii-bit and 16-bit loads and stores, starting with the Alpha 21164a.^[3] Once again, this extension was possible without serious software incompatibilities because the Alpha had always used byte addressing.

See as well [edit]

• Byte addressing

References [edit]

1. ^ Terry Greyzck, Cray Inc. Cray X1 Compiler Challenges (And How We Solved Them)
2. ^ "The Alpha AXP, office 8: Memory access, storing bytes and words and unaligned data". 16 August 2017.
3. ^ "Alpha: The History in Facts and Comments - Alpha 21164 (EV5, EV56) and 21164PC (PCA56, PCA57)".

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Source: https://en.wikipedia.org/wiki/Word_addressing

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